cy62148bn mobl ? 4-mbit (512k x 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number : 001-06517 rev. *d revised june 7, 2010 features 4.5v?5.5v operation low active power ? typical active current: 2.5 ma @ f = 1 mhz ? typical active current:12.5 ma @ f = fmax low standby current automatic power down when deselected ttl-compatible inputs and outputs easy memory expansion with ce and oe features cmos for optimum speed and power available in standard pb-free and non pb-free 32-lead (450-mil) soic and 32-lead tsop ii packages functional description the cy62148bn is a high performance cmos static ram organized as 512k words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ), and tri-state drivers. this device has an automatic power down feature t hat reduces power consumption by more than 99% when deselected. to write to the device, take chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 18 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high for read. under these conditions , the contents of the memory location specified by the address pins appear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) go into a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or a write operation is in progress (ce low and we low). 18 13 a 1 a 4 a 5 a 6 a 7 a 12 a 14 a 16 column decoder row decoder sense amps input buffer power down we oe i/o 0 i/o 1 i/o 2 i/o 3 512 x k8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 2 a 15 a 3 a ce a a 8 a 17 a 9 a 11 a 10 logic block diagram [+] feedback
cy62148bn mobl ? document number : 001-06517 rev. *d page 2 of 10 contents functional description ..................................................... 1 pin configuration ............................................................. 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics over the operating range ..... 4 capacitance [4] ................................................................... 4 ac test loads and waveforms ....................................... 4 switching characteristics [5] over the operating range .5 data retention characteristics (over the operating range) 6 data retention waveform ................................................ 6 switching waveforms ...................................................... 6 read cycle no. 1 [10, 11] ............................................... 6 read cycle no. 2 (oe controlled) [11, 12] ..................... 6 write cycle no. 1 (ce controlled ) [13] ............................. 7 write cycle no. 2 (we controlled, oe high during write) [13, 14] ......................................................................... 7 write cycle no. 3 (we controlled, oe low) [13, 14] .... 8 truth table ........................................................................ 8 ordering information ........................................................ 8 package diagram .............................................................. 9 document history pagesales, solutions, and legal infor- mation .............................................................................. 10 [+] feedback
cy62148bn mobl ? document number : 001-06517 rev. *d page 3 of 10 pin configuration 1 2 3 4 5 6 7 8 9 10 11 14 19 20 24 23 22 21 25 28 27 26 12 13 29 32 31 30 16 15 17 18 a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 we v cc a 15 a 13 a 8 a 9 i/o 7 i/o 6 i/o 5 i/o 4 a 2 i/o 0 i/o 1 i/o 2 ce oe a 10 i/o a 1 a 0 a 11 a 18 top view soic tsop ii gnd i/o 3 a 17 note 1. typical values are measured at v cc = 5v, t a = 25 c, and are included for reference only and are not tested or guaranteed. product portfolio product v cc range speed power dissipation operating i cc (ma) standby i sb2 (a) f = f max typ [1] max min typ max typ [1] max CY62148BNLL 4.5 v 5.0v 5.5v 70 ns 12.5 20 4 20 [+] feedback
cy62148bn mobl ? document number : 001-06517 rev. *d page 4 of 10 maximum ratings exceeding the maximum rating may impair the device?s useful life. user guidelines only and are not tested. storage temperature ............................... ?65 c to +150 c ambient temperature with power applied .......................................... ?55 c to +125 c supply voltage on v cc to relative gnd ........?0.5v to +7.0v dc voltage applied to outputs in high z state [2] ..................................... ?0.5v to v cc +0.5v dc input voltage [2] ................................. ?0.5v to v cc +0.5v current into outputs (low)..... .................................... 20 ma static discharge voltage...............................................2001v (per mil-std-883, method 3015) latch up current ..................................................... >200 ma operating range range ambient temperature [3] v cc industrial ?40 c to +85 c 4.5v?5.5v electrical characteristics over the operating range parameter description test conditions cy62148bn unit min typ [1] max v oh output high voltage i oh = ?1 ma 2.4 v v ol output low voltage i ol = 2.1 ma 0.4 v v ih input high voltage 2.2 v cc +0.3 v v il input low voltage ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v i < v cc , output disabled ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc i out = 0 ma v cc = max., 12.5 20 ma f = 1 mhz 2.5 ma i sb1 automatic ce power down current ? ttl inputs max. v cc , ce > v ih v in ? ? v ih or v in < v il , f = f max 1.5 ma i sb2 automatic ce power down current ? cmos inputs max. v cc , ce ? v cc ? 0.3v, v in ? v cc ? 0.3v, or v in < 0.3v, f =0 4 20 a capacitance [4] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc ? 5.0v 6 pf c out output capacitance 8 pf ac test loads and waveforms notes 2. v il (min.) = ?2.0v for pulse durations of less than 20 ns. 3. t a is the ?instant on? case temperature 4. tested initially and after any design or process changes that may affect these parameters. 5v output 5 pf including jig and scope (b) r2 990 ? (a) 90% 10% 3.0v gnd 90% 10% ?? 3 ns ? 3ns output 639 ? equivalent to: thevenin equivalent 1.77v r1 1800 ? all input pulses 5v output including jig and scope r2 990 ? r1 1800 ? 100 pf [+] feedback
cy62148bn mobl ? document number : 001-06517 rev. *d page 5 of 10 notes 5. test conditions assume signal transition time of 5 ns or less , timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 100-pf load capacitance. 6. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 7. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-stat e voltage. 8. the internal write time of the memory is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of any of these signals can terminate the write. the input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write. switching characteristics [5] over the operating range parameter description cy62148bn unit min max read cycle t rc read cycle time 70 ns t aa address to data valid 70 ns t oha data hold from address change 10 ns t ace ce low to data valid 70 ns t doe oe low to data valid 35 ns t lzoe oe low to low z [6] 5 ns t hzoe oe high to high z [6, 7] 25 ns t lzce ce low to low z [6] 10 ns t hzce ce high to high z [6, 7] 25 ns t pu ce low to power up 0 ns t pd ce high to power down 70 ns write cycle [8] t wc write cycle time 70 ns t sce ce low to write end 60 ns t aw address setup to write end 60 ns t ha address hold from write end 0 ns t sa address setup to write start 0 ns t pwe we pulse width 55 ns t sd data setup to write end 30 ns t hd data hold from write end 0 ns t lzwe we high to low z [6] 5 ns t hzwe we low to high z [6, 7] 25 ns [+] feedback
cy62148bn mobl ? document number : 001-06517 rev. *d page 6 of 10 data retention characteristics (over the operating range) parameter description conditions min typ [1] max unit v dr v cc for data retention 2.0 v i ccdr data retention current no input may exceed v cc + 0.3v v cc = v dr ce > v cc ? 0.3v v in > v cc ? 0.3v or v in < 0.3v 20 a t cdr [4] chip deselect to data retention time 0 ns t r [9] operation recovery time t rc ns data retention waveform 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc switching waveforms read cycle no. 1 [10, 11] read cycle no. 2 (oe controlled) [11, 12] notes 9. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 ms or stable at v cc(min) > 100 ms. 10. device is continuously selected. oe , ce = v il . 11. we is high for read cycle. 12. address valid prior to or coincident with ce transition low. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i sb impedance address data out v cc supply current [+] feedback
cy62148bn mobl ? document number : 001-06517 rev. *d page 7 of 10 write cycle no. 1 (ce controlled) [13] write cycle no. 2 (we controlled, oe high during write) [13, 14] notes 13. if ce goes high simultaneously with we going high, the output remains in a high impedance state. 14. data i/o is high-impedance if oe = v ih . 15. during this period the i/os are in the output state and input signals should not be applied. switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce ce address we data i/o t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 15 t hzce [+] feedback
cy62148bn mobl ? document number : 001-06517 rev. *d page 8 of 10 write cycle no. 3 (we controlled, oe low) [13, 14] switching waveforms (continued) data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 15 t hzce truth table ce oe we i/o 0 ?i/o 7 mode power h x x high z power down standby (i sb ) l l h data out read active (i cc ) l x l data in write active (i cc ) l h h high z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 70 CY62148BNLL-70sxi 51-85081 32-lead (450-mil) molded soic (pb-free) industrial [+] feedback
cy62148bn mobl ? document number : 001-06517 rev. *d page 9 of 10 package diagram figure 1. 32-lead (450 mil) molded soic (51-85081) 51-85081 *c [+] feedback
document number : 001-06517 rev. *d revised june 7, 2010 page 10 of 10 psoc designer? and programmable system-on-chip? are trademarks and psoc? and capsense? are registered trademarks of cypress sem iconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed associat ed companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. more battery life is a trademark, and mobl is a registered trademark, of cypress semiconductor. all products and company names mentioned in this document may be the trademar ks of their respective holders. cy62148bn mobl ? ? cypress semiconductor corporation, 2006-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page document title: cy62148bn mobl ? 4-mbit (512k x 8) static ram document number: 001-06517 rev. ecn no. issue date orig. of change description of change ** 426504 see ecn nxr new data sheet *a 485639 see ecn vkn corrected the typo in the array size in the logic block diagram *b 832320 see ecn nxr removed commercial operating range removed 32-lead reverse tsop ii package from product offering corrected the test condition typo error in electrical characteristics table updated ordering information table *c 2896152 03/18/2010 aju removed inactive parts from ordering information. added table of contents. updated packaging information updated links in sales, solutions, and legal information. *d 2946367 06/07/2010 fsu removed unavailable parts. [+] feedback
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